Redundancy techniques for random access memory (RAM) and read only memory (ROM, EEPROM) type devices are well known. Such conventional techniques typically include redundant rows or columns that can be accessed in lieu of a defective row or column.
However, in other types of devices, such as content addressable memory (CAM) devices, it may be desirable to provide redundancy on a “block” basis. That is, it would be desirable to replace an entire defective block, which includes multiple rows and columns, with a redundant block.
FIG. 8 shows one possible conventional approach to implementing block-wise substitution in a memory device. FIG. 8 shows a mapping circuit 800 that can receive a set of logical block selection signals for each block of a memory device (X0[0:p] to Xn[0:p]) and map each such set to a corresponding set of physical block select signals Y0[0:p] to Ym[0:p]. It is understood that the number of logical blocks is “n+1” and the number of physical blocks is “m+1”. Thus, the number of redundancy blocks “r” is m−n. FIG. 8 also shows an arrangement in which block operations can be further qualified based on some additional number of bits “0 to p” (shown as [0:p]).
In address mapping circuit 800 of FIG. 8, a set of physical block select signals can be mapped to a set of logical block numbers by operation of a switching element, one of which is shown as 802 in FIG. 8. Thus, in the arrangement of FIG. 8 there are (n+1)*(m+1) switching elements. Each switching element (e.g., 802) can be implemented as a full passgate “cross-bar” type circuit, and have a state established by a corresponding state bit value. Typically, the state bit for each switching element 802 can be stored in a register (not shown).
FIGS. 9 and 10 show how a mapping arrangement like that of FIG. 8 can be used to implement redundancy. FIGS. 9 and 10 show examples of a case where the number of logical blocks is eight, and the number of physical blocks is twelve, thus, the number of redundant blocks is four. FIG. 9 shows an example in which no redundancy is needed, and logical blocks 0 to 7 can be mapped to physical blocks 0 to 7, respectively. Thus, switching element states are set to form signals paths illustrated by thicker lines in FIG. 9. In contrast, FIG. 10 shows an example in which all redundant blocks are needed, with signals for logical blocks 2, 5, 6 and 7 being mapped to redundant physical blocks 8, 9, 10 and 11, respectively.
It is understood that FIGS. 9 and 10 show signal paths. However, each such signal path can involve driving two wires (or buses) that extend the full length of the mapping circuit, one in the row direction, the other in the column direction.
While the above approach can provide block-by-block replacement, such an approach may have some drawbacks. First, the area needed for such a switching circuit can be relatively large. For example, in the case of FIG. 8, the circuit 800 must have sufficient area to accommodate (n+1)*(m+1) switching elements. Further, the speed of such a conventional circuit can be adversely affected by the sizable capacitance presented by a wiring path. For example, in the case of FIG. 8, each path can have 2*(n+1)+2*(m+1) diffusion capacitances and a wire capacitance equivalent to n+m+2 switching elements.